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1997 data sheet m pd178p018 mos integrated circuit description the m pd178p018 is a device in which the on-chip mask rom of the m pd178018 is replaced with a one-time prom or eprom. because this device can be programmed by users, it is ideally suited for system evaluation, small-lot and multiple- device production, and early development and time-to-market. the m pd178p018 is a prom version corresponding to the m pd178004, 178006, and 178016. caution the m pd178p018kk-t does not maintain planned reliability when used in your systems mass- produced products. please use only experimentally or for evaluation purposes during trial manu- facture. for more information on functions, refer to the following users manuals. be sure to read them when designing. m pd178018 subseries users manual: u11410e 78k/0 series users manual instruction: u12326e (in preparation) features ? pin-compatible with mask rom version (except for v pp pin) ? internal prom: 60 kbytes ? m pd178p018gc : one-time programmable (ideally suited for small-lot production) ? m pd178p018kk-t : reprogrammable (ideally suited for system evaluation) ? internal high-speed ram: 1024 bytes ? internal expansion ram: 2048 bytes ? buffer ram: 32 bytes ? can be operated in the same power supply voltage as the mask rom version (during pll operation: v dd = 4.5 to 5.5 v) the electrical specifications (power supply current, etc.) and pll analog specifications of the m pd178p018 differ from that of mask rom versions. so, these differences should be considered and verified before application sets are mass-produced. in this document, the term prom is used in parts common to one-time prom versions and eprom versions. document no. u12298ej1v0ds00 (1st edition) date published may 1997 n printed in japan 8-bit single-chip microcontroller the information in this document is subject to change without notice.
m pd178p018 2 applications car stereo, home stereo systems ordering information part number package internal rom quality grade m pd178p018gc-3b9 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) one-time prom standard m pd178p018kk-t note 80-pin ceramic wqfn (14 14 mm, 0.65-mm pitch) eprom not applicable note under planning please refer to "quality grade on nec semiconductor devices" (document number c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. m pd178018 subseries expansion pd178018 subseries 80 pins prom: 60 kb ram: 3 kb pd178p018 80 pins rom: 60 kb ram: 3 kb pd178018 80 pins rom: 48 kb ram: 3 kb pd178016 80 pins rom: 48 kb ram: 1 kb pd178006 80 pins rom: 32 kb ram: 1 kb pd178004 m m m m m m
m pd178p018 3 function description item function internal memory ? prom : 60 kbytes ? ram high-speed ram : 1024 bytes expansion ram : 2048 bytes buffer ram : 32 bytes general register 8 bits 32 registers (8 bits 8 registers 4 banks) instruction cycle with variable instruction execution time function 0.44 m s/0.88 m s/1.78 m s/3.56 m s/7.11 m s/14.22 m s (with 4.5-mhz crystal resonator) instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits 8 bits) ? bit manipulate (set, reset, test, boolean operation) ? bcd adjust, etc. i/o port total : 62 pins ? cmos input : 1 pin ? cmos i/o : 54 pins ? n-ch open-drain i/o : 4 pins ? n-ch open-drain output : 3 pins a/d converter 8-bit resolution 6 channels serial interface ? 3-wire/sbi/2-wire/i 2 c bus note mode selectable : 1 channel ? 3-wire serial i/o mode (with automatic transmit/receive function of up to 32 bytes) : 1 channel timer ? basic timer (timer carry ff (10 hz)) : 1 channel ? 8-bit timer/event counter : 2 channels ? 8-bit timer (d/a converter: pwm output) : 1 channel ? watchdog timer : 1 channel buzzer (beep) output 1.5 khz, 3 khz, 6 khz vectored maskable interrupt internal: 8, external: 7 interrupt non-maskable interrupt internal: 1 software interrupt internal: 1 test input internal: 1 pll frequency division mode two types synthesizer ? direct division mode (vcol pin) ? pulse swallow mode (vcoh and vcol pins) reference frequency 11 types selectable by program (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50 khz) charge pump error out output: 2 phase comparator unlock detectable by program frequency counter ? frequency measurement ? amifc pin: for 450-khz count ? fmifc pin: for 450-khz/10.7-mhz count d/a converter (pwm output) 8-/9-bit resolution 3 channels (shared by 8-bit timer) standby function ? halt mode ? stop mode note when using the i 2 c bus mode (including when this mode is implemented by program without using the peripheral hardware), consult your local nec sales representative when you place an order for mask. (1/2)
m pd178p018 4 item function reset ? reset via the reset pin ? internal reset by watchdog timer ? reset by power-on clear circuit (3-value detection) ? detection of less than 4.5 v note (cpu clock: f x ) ? detection of less than 3.5 v note (cpu clock: f x /2 or less and on power application) ? detection of less than 2.5 v note (in stop mode) power supply voltage ? v dd = 4.5 to 5.5 v (with pll operating) ?v dd = 3.5 to 5.5 v (with cpu operating, cpu clock: f x /2 or less) ?v dd = 4.5 to 5.5 v (with cpu operating, cpu clock: f x ) package ? 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) ? 80-pin ceramic wqfn (14 14 mm, 0.65-mm pitch) note these voltage values are maximum values. the reset is actually executed at a voltage lower than these values. (2/2)
m pd178p018 5 pin configurations (top view) (1) normal operating mode ? 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) m pd178p018gc-3b9 ? 80-pin ceramic wqfn (14 14 mm, 0.65-mm pitch) m pd178p018kk-t cautions 1. connect the v pp pin to gnd directly. 2. connect the v dd port and v dd pll pins to v dd . 3. connect the gndport and gndpll pins to gnd. 4. connect each of the regosc and regcpu pins to gnd via a 0.1- m f capacitor. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p132/pwm0 p133/pwm1 p134/pwm2 p40 p41 p42 gndport v dd port p43 p44 p45 p46 p47 amifc fmifc v dd pll vcoh vcol gndpll eo0 eo1 v pp p50 p51 p52 p53 p37 p36/beep p35 p34/ti2 p33/ti1 p32 p31 p30 p67 p66 p65 p64 p63 p62 p61 p60 p57 p56 p55 p54 reset v dd regosc x1 x2 gnd regcpu p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1 p00/intp0 p125 p124 p123 p122 p121 p120
m pd178p018 6 amifc : am intermediate frequency counter input ani0 to ani5 : a/d converter input beep : buzzer output busy : busy output eo0, eo1 : error out output fmifc : fm intermediate frequency counter input gnd : ground gndpll : pll ground gndport : port ground intp0 to intp6 : interrupt inputs p00 to p06 : port 0 p10 to p15 : port 1 p20 to p27 : port 2 p30 to p37 : port 3 p40 to p47 : port 4 p50 to p57 : port 5 p60 to p67 : port 6 p120 to p125 : port 12 p132 to p134 : port 13 pwm0 to pwm2 : pwm output regcpu : regulator for cpu power supply regosc : regulator for oscillator reset : reset input sb0, sb1 : serial data bus input/output sck0, sck1 : serial clock input/output scl : serial clock input/output sda0, sda1 : serial data input/output si0, si1 : serial data input so0, so1 : serial data output stb : strobe output ti1, ti2 : timer clock input vcol, vcoh : local oscillation input v dd : power supply v dd pll : pll power supply v dd port : port power supply v pp : programming power supply x1, x2 : crystal resonator connection
m pd178p018 7 (2) prom programming mode ? 80-pin plastic qfp (14 14 mm) m pd178p018gc-3b9 ? 80-pin ceramic wqfn m pd178p018kk-t note note under planning cautions 1. (l) : individually connect to gnd via a pull-down resistor. 2. gnd : connect to gnd. 3. reset : set to the low level. 4. open : leave open. a0 to a16 : address bus ce : chip enable d0 to d7 : data bus gnd : ground oe : output enable pgm : program reset : reset v dd : power supply v pp : programming power supply 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a0 a1 a2 gnd v dd a3 a4 a5 a6 a7 v dd gnd v pp a8 a16 a10 a11 (l) open 60 59 58 57 56 55 54 53 52 51 d7 d6 d5 d4 d3 d2 d1 d0 ce oe a15 a14 a13 a12 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 (l) (l) (l) (l) open reset v dd v dd (l) open gnd v dd pgm (l) a9 (l) (l)
m pd178p018 8 block diagram 8-bit timer/ event counter 1 8-bit timer/ event counter 2 8-bit timer3 watchdog timer basic timer serial interface 0 serial interface 1 a/d converter interrupt control buzzer output system control ram (3072 bytes) 78k/0 cpu core prom (60 k bytes) 6 6 8 8 8 8 8 6 3 6 7 3 p00 p01 to p06 d/a converter (pwm) pwm0/p132 to pwm2/p134 frequency counter pll voltage regulator pll voltage regulator ti1/p33 ti2/p34 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 reset x1 x2 v dd port gndport v dd reset cpu peripheral regosc regcpu gnd v osc v cpu ani0/p10 to ani5/p15 intp0/p00 to intp6/p06 beep/p36 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 12 port 13 p10 to p15 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p120 to p125 p132 to p134 amifc fmifc eo0 eo1 vcol vcoh v dd pll gndpll v pp
m pd178p018 9 contents 1. pin function list ............................................................................................................ .............. 10 1.1 pins in normal operating mode ............................................................................................. .. 10 1.2 pins in prom programming mode ........................................................................................... 12 1.3 pins input/output circuits and recommended connection of unused pins ...................... 13 2. prom programming ........................................................................................................... .......... 16 2.1 operating modes ........................................................................................................... ............. 16 2.2 prom write procedure ...................................................................................................... ....... 18 2.3 prom read procedure ....................................................................................................... ....... 22 3. program erasure ( m pd178p018kk-t only) ....................................................................... 23 4. opaque film on erasure window ( m pd178p018kk-t only) ........................................ 23 5. one-time prom version screening .................................................................................... 23 6. electrical specifications .................................................................................................... .. 24 7. package drawings ............................................................................................................. ........ 46 8. recommended soldering conditions ................................................................................. 48 appendix a. development tools ................................................................................................ 4 9 appendix b. related documents ................................................................................................ 5 3
10 m pd178p018 1. pin function list 1.1 pins in normal operating mode (1) port pins pin name i/o function after reset alternate function p00 input port 0. input only input intp0 p01 to p06 i/o 7-bit input/output port. input/output mode can be specified bit-wise. input intp1 to intp6 p10 to p15 i/o port 1. input ani0 to ani5 6-bit input/output port. input/output mode can be specified bit-wise. p20 i/o port 2. input si1 p21 8-bit input/output port. so1 p22 input/output mode can be specified bit-wise. sck1 p23 stb p24 busy p25 si0/sb0/sda0 p26 so0/sb1/sda1 p27 sck0/scl p30 to p32 i/o port 3. input p33 8-bit input/output port. ti1 p34 input/output mode can be specified bit-wise. ti2 p35 p36 beep p37 p40 to p47 i/o port 4. input 8-bit input/output port. input/output mode can be specified in 8-bit units. test input flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5. input 8-bit input/output port. input/output mode can be specified bit-wise. p60 to p63 i/o port 6. middle voltage n-ch open-drain input 8-bit input/output port. input/output port. p64 to p67 input/output mode can be leds can be driven directly. specified bit-wise. p120 to i/o port 12. input p125 6-bit input/output port. input/output mode can be specified bit-wise. p132 to output port 13. pwm0 to p134 3-bit output port. pwm2 n-ch open-drain output port.
11 m pd178p018 pin name i/o function after reset alternate function intp0 to input external maskable interrupt inputs with specifiable valid edges (rising input p00 to p06 intp6 edge, falling edge, both rising and falling edges). si0 input serial interface serial data input input p25/sb0/sda0 si1 p20 so0 output serial interface serial data output input p26/sb1/sda1 so1 p21 sb0 i/o serial interface serial data input/output input p25/si0/sda0 sb1 p26/so0/sda1 sda0 p25/si0/sb0 sda1 p26/so0/sb1 sck0 i/o serial interface serial clock input/output input p27/scl sck1 p22 scl p27/sck0 stb output serial interface automatic transmit/receive strobe output input p23 busy input serial interface automatic transmit busy input input p24 ti1 input external count clock input to 8-bit timer (tm1) input p33 ti2 external count clock input to 8-bit timer (tm2) p34 beep output buzzer output input p36 ani0 to ani5 input a/d converter analog input input p10 to p15 pwm0 to output pwm output p132 to p134 pwm2 eo0, eo1 output error out output from charge pump of the pll frequency synthesizer vcol input inputs pll local band oscillation frequency (in hf, mf mode). vcoh input inputs pll local band oscillation frequency (in vhf mode). amifc input inputs am intermediate frequency counter. fmifc input inputs fm intermediate frequency counter. reset input system reset input x1 input crystal resonator connection for system clock oscillation x2 regosc regulator for oscillator. connected to gnd via a 0.1- m f capacitor. regcpu regulator for cpu power supply. connected to gnd via a 0.1- m f capacitor. v dd positive power supply gnd ground v dd port positive power supply for port block gndport ground for port block v dd pll positive power supply for pll gndpll ground for pll (2) non-port pins (1 of 2)
12 m pd178p018 (2) non-port pins (2/2) 1.2 pins in prom programming mode pin name i/o function after reset alternate function v pp high-voltage applied during program write/verification. connected directly to gnd in normal operating mode. pin name i/o function reset input prom programming mode setting when +5 v or +12.5 v is applied to v pp pin and a low-level signal is applied to the reset pin, this chip is set in the prom programming mode. v pp input prom programming mode setting and high-voltage applied during program write/verification. a0 to a16 input address bus d0 to d7 i/o data bus ce input prom enable input/program pulse input oe input read strobe input to prom pgm input program/program inhibit input in prom programming mode. v dd positive power supply gnd ground potential
13 m pd178p018 pin name i/o circuit type i/o recommended connections of unused pins p00/intp0 2 input connected to gnd or gndport p01/intp1 to p06/intp6 8 i/o set in general-purpose input port mode by software and p10/ani0 to p15/ani5 11-a individually connected to v dd , v dd port, gnd, or gndport p20/si1 8 via a resistor. p21/so1 5 p22/sck1 8 p23/stb 5 p24/busy 8 p25/si0/sb0/sda0 10 p26/so0/sb1/sda1 p27/sck0/scl p30 to p32 5 p33/ti1, p34/ti2 8 p35 5 p36/beep p37 p40 to p47 5-g p50 to p57 5 p60 to p63 13 p64 to p67 5 p120 to p125 p132/pwm0 to p134/pwm2 19 output set to the low-level output by software and open eo0 dts-eo1 open eo1 dts-eo2 vcol, vcoh dts-amp input set to disabled status by software and open amifc, fmifc v pp connected to gnd or gndport directly 1.3 pins input/output circuits and recommended connection of unused pins table 1-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. refer to figure 1-1 for the configuration of the input/output circuit of each type. table 1-1. type of i/o circuit of each pin
14 m pd178p018 figure 1-1. types of pin input/output circuits (1/2) remark all v dd and gnd in the above figures are the positive power supply and ground potential of the ports, and should be read as v dd port and gndport, respectively. in data output disable p-ch in/out v dd n-ch data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch data output disable p-ch in/out v dd n-ch open drain data output disable p-ch in/out v dd n-ch input enable + p-ch n-ch type 2 type 8 type 5 schmitt-triggered input with hysteresis characteristics type 10 type 5-g type 11-a comparator v ref (threshold voltage)
15 m pd178p018 figure 1-1. types of pin input/output circuits (2/2) remark all v dd and gnd in the above figures are the positive power supply and ground potential of the ports, and should be read as v dd port and gndport, respectively. in data output disable in/out n-ch p-ch v dd pll v dd pll n-ch gndpll dw up out out n-ch dw up p-ch out v dd pll gndpll n-ch type 13 type dts-eo2 type 19 middle-voltage input buffer type dts-eo1 type dts-amp
m pd178p018 16 pin reset v pp v dd ce oe pgm d0 to d7 operating mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high-impedance byte write l h l data input program verify l l h data output program inhibit x h h high-impedance xll read +5 v +5 v l l h data output output disable l h x high-impedance standby h x x high-impedance remark x : l or h 2. prom programming the m pd178p018 has an internal 60-kbyte prom as a program memory. for programming, set the prom programming mode with the v pp and reset pins. for the connection of unused pins, refer to pin configura- tions (top view) (2) prom programming mode. caution programs must be written in addresses 0000h to efffh (the last address efffh must be specified). they cannot be written by a prom writer which cannot specify the write address. 2.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and a low-level signal is applied to the reset pin, the prom programming mode is set. this mode will become the operating mode as shown in table 2-1 when the ce, oe, and pgm pins are set as shown. further, when the read mode is set, it is possible to read the contents of the prom. table 2-1. operating modes of prom programming
m pd178p018 17 (1) read mode read mode is set if ce = l and oe = l are set. (2) output disable mode data output becomes high-impedance, and is in the output disable mode, if oe = h is set. therefore, it allows data to be read from any device by controlling the oe pin, if multiple m pd178p018s are connected to the data bus. (3) standby mode standby mode is set if ce = h is set. in this mode, data outputs become high-impedance irrespective of the oe status. (4) page data latch mode page data latch mode is set if ce = h, pgm = h, and oe = l are set at the beginning of page write mode. in this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) page write mode after 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the pgm pin with ce = h and oe = h. then, program verification can be performed, if ce = l and oe = l are set. if programming is not performed by a one-time program pulse, x times (x 10) write and verification operations should be executed repeatedly. (6) byte write mode byte write is executed when a 0.1-ms program pulse (active low) is applied to the pgm pin with ce = l and oe = h. then, program verification can be performed if oe = l is set. if programming is not performed by a one-time program pulse, x times (x 10) write and verification operations should be executed repeatedly. (7) program verify mode program verify mode is set if ce = l, pgm = h, and oe = l are set. in this mode, check if a write operation is performed correctly after the write. (8) program inhibit mode program inhibit mode is used when the oe pin, v pp pin, and d0 to d7 pins of multiple m pd178p018s are connected in parallel and a write is performed to one of those devices. when a write operation is performed, the page write mode or byte write mode described above is used. at this time, a write is not performed to a device which has the pgm pin driven high.
m pd178p018 18 2.2 prom write procedure figure 2-1. page program mode flow chart remark g = start address n = program last address start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 0.1-ms program pulse x = 10? no fail verify 4 bytes pass address = n? no yes v dd = 4.5 to 5.5 v, v pp = v dd verify all bytes pass fail all pass write end defective product yes address = address + 1
m pd178p018 19 figure 2-2. page program mode timing page data latch program verify page program a2 to a16 a0, a1 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il data input data output
m pd178p018 20 figure 2-3. byte program mode flow chart remark g = start address n = program last address start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 x = x + 1 0.1-ms program pulse address = address + 1 x = 10? no yes fail vefity pass address = n? no yes v dd = 4.5 to 5.5 v, v pp = v dd verify all bytes pass fail all pass write end defective product
m pd178p018 21 figure 2-4. byte program mode timing cautions 1. v dd should be applied before v pp , and removed after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. reliability may be adversely affected if removal/reinsertion is performed while +12.5 v is being applied to v pp . program program verify a0 to a16 d0 to d7 data input data output v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il
m pd178p018 22 2.3 prom read procedure the contents of prom are readable to the external data bus (d0 to d7) according to the read procedure shown below. (1) fix the reset pin at low level, supply +5 v to the v pp pin, and connect all other unused pins as shown in pin configurations (top view) (2) prom programming mode. (2) supply +5 v to the v dd and v pp pins. (3) input address of read data into the a0 to a16 pins. (4) read mode (5) output data to d0 to d7 pins. the timings of the above steps (2) to (5) are shown in figure 2-5. figure 2-5. prom read timings address input a0 to a16 data output d0 to d7 oe (input) ce (input) hi-z hi-z
23 m pd178p018 3. program erasure ( m pd178p018kk-t only) the m pd178p018kk-t is capable of erasing (ffh) the data written in a program memory and rewriting. to erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400 nm. normally, irradiate ultraviolet rays of 254-nm wavelength. the amount of exposure required to completely erase the programmed data is as follows: ? uv intensity x erasure time: 30 w?s/cm 2 or more ? erasure time: 40 min. or more (when a uv lamp of 12,000 m w/cm 2 is used. however, a longer time may be needed because of deterioration in performance of the uv lamp, soiled erasure window, etc.) when erasing the contents of the data, set up the uv lamp within 2.5 cm from the erasure window. further, if a filter is provided for a uv lamp, irradiate the ultraviolet rays after removing the filter. 4. opaque film on erasure window ( m pd178p018kk-t only) to protect from an intentional erasure by rays other than that of the lamp for erasing eprom contents, or to protect internal circuit other than eprom from misoperating by rays, cover the erasure window with an opaque film when eprom contents erasure is not performed. 5. one-time prom version screening the one-time prom version ( m pd178p018gc-3b9) cannot be tested completely by nec before it is shipped, because of its structure. it is recommended to perform screening to verify prom after writing necessary data and performing high-temperature storage under the condition below. storage temperature storage time 125 c 24 hours
24 m pd178p018 6. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions ratings unit power supply voltage v dd C0.3 to +7.0 v v pp C0.3 to +13.5 v input voltage v i1 excluding p60 to p63 C0.3 to v dd + 0.3 v v i2 p60 to p63 n-ch open-drain C0.3 to +16 v v i3 a9 prom programming mode C0.3 to +13.5 v output voltage v o C0.3 to v dd + 0.3 v output withstand v bds p132 to p134 n-ch open-drain 16 v voltage analog input voltage v an p10 to p15 analog input pin C0.3 to v dd + 0.3 v output current high i oh 1 pin C10 ma p01 to p06, p30 to p37, p56, p57, p60 to p67, C15 ma p120 to p125 total p10 to p15, p20 to p27, p40 to p47, p50 to p55, C15 ma p132 to p134 total output current low i ol note 1 pin peak value 15 ma r.m.s. value 7.5 ma operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c note r.m.s. (root mean square) value should be calculated as follows: [r.m.s value] = [peak value] ? duty caution product quality may suffer if the absolute maximum rating is exceeded for even a single parameter even momentarily. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. remark the characteristics of an alternate-function pin and a port pin are the same unless specified otherwise. recommended supply voltage ranges (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit power supply voltage v dd1 during cpu operation and pll operation. 4.5 5.5 v v dd2 while the cpu is operating and the pll is stopped. 3.5 5.5 v cycle time: t cy 3 0.89 m s v dd3 while the cpu is operating and the pll is stopped. 4.5 5.5 v cycle time: t cy = 0.44 m s remark t cy : cycle time (minimum instruction execution time)
25 m pd178p018 dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit input voltage high v ih1 p10 to p15, p21, p23, 0.7v dd v dd v p30 to p32, p35 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125 v ih2 p00 to p06, p20, p22, 0.85v dd v dd v p24 to p27, p33, p34, reset v ih3 p60 to p63 0.7v dd 15 v (n-ch open-drain) input voltage low v il1 p10 to p15, p21, p23, 0 0.3v dd v p30 to p32, p35 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125 v il2 p00 to p06, p20, p22, 0 0.15v dd v p24 to p27, p33, p34, reset v il3 p60 to p63 4.5 v v dd 5.5 v 0 0.3v dd v (n-ch open-drain) 3.5 v v dd < 4.5 v 0 0.2v dd v output voltage high v oh1 4.5 v v dd 5.5 v, v dd C 1.0 v i oh = C1 ma 3.5 v v dd < 4.5 v, v dd C 0.5 v i oh = C100 m a output voltage low v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v i oh = 15 ma p01 to p06, p10 to p15, v dd = 4.5 to 5.5 v, 0.4 v p20 to p27, p30 to p37, i ol = 1.6 ma p40 to p47, p64 to p67, p120 to p125, p132 to p134 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2v dd v n-ch open-drain pulled-up (r = 1 k w ) remark the characteristics of an alternate-function pin and a port pin are the same unless specified otherwise. (1/3)
26 m pd178p018 dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) note when an input instruction is executed, the low-level input leakage current for p60 to p63 becomes C200 m a (max.) only in one clock cycle (at no wait). it remains at C3 m a (max.) for other than an input instruction. remark the characteristics of an alternate-function pin and a port pin are the same unless specified otherwise. reference characteristics (t a = 25 c, v dd = 5 v) parameter symbol test conditions min. typ. max. unit input leakage i lih1 p00 to p06, p10 to p15, v in = v dd 3 m a current high p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125, reset i lih2 p60 to p63 v in = 15 v 80 m a input leakage i lil1 p00 to p06, p10 to p15, v in = 0 v C3 m a current low p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p120 to p125, reset i lil2 p60 to p63 C3 note m a output leakage i loh p132 to p134 v out = 15 v 3 m a current high output leakage i lol p132 to p134 v out = 0 v C3 m a current low output off leak i lof eo0, eo1 v out = v dd , 1 m a current v out = 0 v parameter symbol test conditions min. typ. max. unit output current high i oh1 eo0 v out = v dd C 1 v C4 ma eo1 (eocon0 = 1) C6 ma eo1 (eocon0 = 0) C2 ma output current low i ol1 eo0 v out = 1 v 6 ma eo1 (eocon0 = 1) 8 ma eo1 (eocon0 = 0) 3 ma (2/3) (1/2)
27 m pd178p018 dc characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit power supply i dd1 while the cpu is operating t cy = 0.89 m s note 2 2.5 15 ma current note 1 and the pll is stopped i dd2 f x = 4.5-mhz operation t cy = 0.44 m s note 3 4.0 27 ma v dd = 4.5 to 5.5 v i dd3 while the cpu is operating t cy = 0.89 m s note 2 14ma and the pll is stopped halt mode. i dd4 pin x1 sine wave t cy = 0.44 m s note 3 1.6 6 ma input v in = v dd v dd = 4.5 to 5.5 v f x = 4.5-mhz operation data hold v ddr1 when the crystal is oscillating t cy = 0.44 m s 4.5 5.5 v power supply v ddr2 t cy = 0.89 m s 3.5 5.5 v voltage v ddr3 when the crystal oscillation is stopped 2.7 5.5 v when power off by power on clear is detected data hold i ddr1 while the crystal oscillation t a = 25 c, v dd = 5v 2 4 m a power supply current i ddr2 is stopped 230 m a notes 1. the port current is not included. 2. when the processor clock control register (pcc) is set at 00h, and the oscillation mode select register (osms) is set to 00h. 3. when pcc is set to 00h and osms is set to 01h. remarks 1. t cy : cycle time (minimum instruction execution time) 2. fx: system clock oscillation frequency. reference characteristics (t a = 25 c, v dd = 5 v) parameter symbol test conditions min. typ. max. unit power supply i dd5 during cpu operation t cy = 0.44 m s note 7ma current and pll operation. vcoh pin sine wave input f in = 130 mhz, v in = 0.15 v p-p note when the processor clock control register (pcc) is set to 00h, and the oscillation mode select register (osms) is set to 01h. remark t cy : cycle time (minimum instruction execution time) (3/3) (2/2)
28 m pd178p018 ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit cycle time t cy f xx = f x /2 note 1 , f x = 4.5-mhz operation 0.89 14.22 m s (minimum instruction f xx = f x note 2 , 4.5 v dd 5.5 v 0.44 7.11 m s execution time) f x = 4.5-mhz operation 3.5 v dd < 4.5 v 0.89 7.11 m s ti1, ti2 input f ti 4.5 v dd 5.5 v 0 4.5 mhz frequency 3.5 v v dd < 4.5 v 0 275 khz ti1, ti2 input high/ t tih , 4.5 v dd 5.5 v 111 ns low-level width t til 3.5 v v dd < 4.5 v 1.8 m s interrupt input high/ t inth , intp0 8/f sam note 3 m s low-level width t intl intp1 to intp6 10 m s reset low-level t rsl 10 m s width notes 1. when the oscillation mode selection register (osms) is set to 00h. 2. when osms is set to 01h. 3. in combination with bits 0 (scs0) and 1 (scs1) of the sampling clock select register (scs), selection of f sam is possible among f xx /2 n , f xx /32, f xx /64, and f xx /128 (when n = 0 to 4). remarks 1. f xx : system clock frequency (f x or f x /2) 2. f x : system clock oscillation frequency t cy vs v dd (when system clock f xx is operating at f x /2) t cy vs v dd (when system clock f xx is operating at f x ) cycle time t cy [ m s] cycle time t cy [ m s] 60 10 2.0 1.0 0.5 0.4 0 123456 power supply voltage v dd [v] power supply voltage v dd [v] 60 10 2.0 1.0 0.5 0.4 0 123456 operation guaranteed range operation guaranteed range
29 m pd178p018 (2) serial interface (t a = C40 to +85 c, v dd = 3.5 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy1 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck0 high-/low-level width t kh1 , 4.5 v v dd 5.5 v t kcy1 /2 C 50 ns t kl1 3.5 v v dd < 4.5 v t kcy1 /2 C 100 ns si0 setup time (to sck0 - )t sik1 4.5 v v dd 5.5 v 100 ns 3.5 v v dd < 4.5 v 150 ns si0 hold time (from sck0 - )t ksi1 400 ns so0 output delay time from sck0 t kso1 c = 100 pf note 300 ns note c is the load capacitance of the so0 output line. (ii) 3-wire serial i/o mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy2 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck0 high-/low-level width t kh2 , 4.5 v v dd 5.5 v 400 ns t kl2 3.5 v v dd < 4.5 v 800 ns si0 setup time (to sck0 - )t sik2 100 ns si0 hold time (from sck0 - )t ksi2 400 ns so0 output delay time from sck0 t kso2 c = 100 pf note 300 ns sck0 rising or falling edge time t r2 , t f2 1000 ns note c is the load capacitance of the so0 output line.
30 m pd178p018 (iii) sbi mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy3 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 3200 ns sck0 high-/low-level width t kh3 , 4.5 v v dd 5.5 v t kcy3 /2 C 50 ns t kl3 3.5 v v dd < 4.5 v t kcy3 /2 C 150 ns sb0, sb1 setup time (to sck0 - )t sik3 4.5 v v dd 5.5 v 100 ns 3.5 v v dd < 4.5 v 300 ns sb0, sb1 hold time (from sck0 - ) t ksi3 t kcy3 /2 ns sb0, sb1 output delay time from t kso3 r = 1 k w 4.5 v v dd 5.5 v 0 250 ns sck0 c = 100 pf note 3.5 v v dd < 4.5 v 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy3 ns sck0 from sb0, sb1 t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines. (iv) sbi mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy4 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 3200 ns sck0 high-/low-level width t kh4 , 4.5 v v dd 5.5 v 400 ns t kl4 3.5 v v dd < 4.5 v 1600 ns sb0, sb1 setup time (to sck0 - )t sik4 4.5 v v dd 5.5 v 100 ns 3.5 v v dd < 4.5 v 300 ns sb0, sb1 hold time (from sck0 - ) t ksi4 t kcy4 /2 ns sb0, sb1 output delay time from t kso4 r = 1 k w 4.5 v v dd 5.5 v 0 300 ns sck0 c = 100 pf note 3.5 v v dd < 4.5 v 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy4 ns sck0 from sb0, sb1 t sbk t kcy4 ns sb0, sb1 high-level width t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck0 rising or falling edge time t r4 , t f4 1000 ns note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines.
31 m pd178p018 (v) 2-wire serial i/o mode (sck0 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k w 1600 ns sck0 high-level width t kh5 c = 100 pf note t kcy5 /2 C 160 ns sck0 low-level width t kl5 4.5 v v dd 5.5 v t kcy5 /2 C 50 ns 3.5 v v dd < 4.5 v t kcy5 /2 C 100 ns sb0, sb1 setup time (to sck0 - )t sik5 4.5 v v dd 5.5 v 300 ns 3.5 v v dd < 4.5 v 350 ns 400 ns sb0, sb1 hold time (from sck0 - ) t ksi5 600 ns sb0, sb1 output delay time from t kso5 0 300 ns sck0 note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines. (vi) 2-wire serial i/o mode (sck0 ... external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy6 1600 ns sck0 high-level width t kh6 650 ns sck0 low-level width t kl6 800 ns sb0, sb1 setup time (to sck0 - )t sik6 100 ns sb0, sb1 hold time (from sck0 - ) t ksi6 t kcy6 /2 ns sb0, sb1 output delay time from t kso6 r = 1 k w 4.5 v v dd 5.5 v 0 300 ns sck0 c = 100 pf note 3.5 v v dd < 4.5 v 0 500 ns sck0 at rising or falling edge time t r6 , t f6 1000 ns note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines.
32 m pd178p018 (vii) i 2 c bus mode (scl ... internal clock output) parameter symbol test conditions min. typ. max. unit scl cycle time t kcy7 r = 1 k w 10 m s scl high-level width t kh7 c = 100 pf note t kcy7 C 160 ns scl low-level width t kl7 t kcy7 C 50 ns sda0, sda1 setup time (to scl - ) t sik7 200 ns sda0, sda1 hold time t ksi7 0ns (from scl ) sda0, sda1 output delay time t kso7 4.5 v v dd 5.5 v 0 300 ns (from scl ) 3.5 v v dd < 4.5 v 0 500 ns sda0, sda1 from scl - or t ksb 200 ns sda0, sda1 - from scl - scl from sda0, sda1 t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns note r and c are the load resistance and load capacitance of the scl, sda0, and sda1 output lines. (viii) i 2 c bus mode (scl ... external clock input) parameter symbol test conditions min. typ. max. unit scl cycle time t kcy8 1000 ns scl high-/low-level width t kh8, t kl8 400 ns sda0, sda1 setup time (to scl - ) t sik8 200 ns sda0, sda1 hold time t ksi8 0ns (from scl ) sda0, sda1 output delay time t kso8 r = 1 k w 4.5 v v dd 5.5 v 0 300 ns from scl c = 100 pf note 3.5 v v dd < 4.5 v 0 500 ns sda0, sda1 from scl - or t ksb 200 ns sda0, sda1 - from scl - scl from sda0, sda1 t sbk 400 ns sda0, sda1 high-level width t sbh 500 ns scl rising or falling edge time t r8 , t f8 1000 ns note r and c are the load resistance and load capacitance of the sda0 and sda1 output lines.
33 m pd178p018 (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck1 high-/low-level width t kh9 , 4.5 v v dd 5.5 v t kcy9 /2 C 50 ns t kl9 3.5 v v dd < 4.5 v t kcy9 /2 C 100 ns si1 setup time (to sck1 - )t sik9 4.5 v v dd 5.5 v 100 ns 3.5 v v dd < 4.5 v 150 ns si1 hold time (from sck1 - )t ksi9 400 ns so1 output delay time (from sck1 ) t kso9 c = 100 pf note 300 ns parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck1 high-/low-level width t kh10 , 4.5 v v dd 5.5 v 400 ns t kl10 3.5 v v dd < 4.5 v 800 ns si1 setup time (to sck1 - )t sik10 100 ns si1 hold time (from sck1 - )t ksi10 400 ns so1 output delay time (from sck1 )t kso10 c = 100 pf note 300 ns sck1 rising or falling edge time t r10 , t f10 1000 ns note c is the load capacitance of the so1 output line. (ii) 3-wire serial i/o mode (sck1 ... external clock input) note c is the load capacitance of the so1 output line.
34 m pd178p018 (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy11 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck1 high-/low-level width t kh11 , 4.5 v v dd 5.5 v t kcy11 /2 C 50 ns t kl11 3.5 v v dd < 4.5 v t kcy11 /2 C 100 ns si1 setup time (to sck1 - )t sik11 4.5 v v dd 5.5 v 100 ns 3.5 v v dd < 4.5 v 150 ns si1 hold time (from sck1 - )t ksi11 400 ns so1 output delay time (from sck1 )t kso11 c = 100 pf note 300 ns stb - from sck1 - t sbd t kcy11 /2 C 100 t kcy11 /2 + 100 ns strobe signal high-level width t sbw t kcy11 C 30 t kcy11 + 30 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal detection timing) 3.5 v v dd < 4.5 v 150 ns sck1 from busy inactive t sps 2t kcy11 ns note c is the load capacitance of the so1 output line. (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1 ... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy12 4.5 v v dd 5.5 v 800 ns 3.5 v v dd < 4.5 v 1600 ns sck1 high-/low-level width t kh12 , 4.5 v v dd 5.5 v 400 ns t kl12 3.5 v v dd < 4.5 v 800 ns si1 setup time (to sck1 - )t sik12 100 ns si1 hold time (from sck1 - )t ksi12 400 ns so1 output delay time (from sck1 )t kso12 c = 100 pf note 300 ns sck1 rising or falling edge time t r12 , t f12 1000 ns note c is the load capacitance of the so1 output line.
35 m pd178p018 ac timing test point (excluding x1 input) ti timing interrupt input timing reset input timing 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd 1/f ti t til t tih ti1, ti2 intp0 to intp6 t intl t inth reset t rsl
36 m pd178p018 serial transfer timing 3-wire serial i/o mode: remark m = 1, 2, 9, 10 n = 2, 10 sbi mode (bus release signal transfer): sck0, sck1 t rn t klm t kcym t khm t fn si0, si1 input data t ksim t sikm output data t ksom so0, so1 t ksb t sbl t sbh t sbk t kl3, 4 t kh3, 4 t f4 t r4 t sik3, 4 t ksi3, 4 t kso3, 4 sck0 sb0, sb1 t kcy3, 4
37 m pd178p018 sbi mode (command signal transfer): 2-wire serial i/o mode: i 2 c bus mode: t ksb t sbk t f4 t r4 t sik3, 4 t ksi3, 4 t kso3, 4 sck0 sb0, sb1 t kl3, 4 t kh3, 4 t kcy3, 4 t f6 t r6 sck0 sb0, sb1 t kl5, 6 t kh5, 6 t kcy5, 6 t ksi5, 6 t sik5, 6 t kso5, 6 scl sda0, sda1 t f8 t kcy7, 8 t kh7, 8 t kso7, 8 t sik7, 8 t ksi7, 8 t sbk t sbh t kl7, 8 t r8 t ksb t sbk t ksb
38 m pd178p018 3-wire serial i/o mode with automatic transmit/receive function: 3-wire serial i/o mode with automatic transmit/receive function (busy processing): note the signal is not actually driven low here; it is shown as such to indicate the timing. stb sck1 si1 so1 d2 d1 d0 d2 d1 d0 d7 d7 t sik11, 12 t ksi11, 12 t kso11, 12 t kh11, 12 t f12 t r12 t kl11, 12 t kcy11, 12 t sbd t sbw t byh t sps t bys 789 note 10 note 10+n note 1 sck1 busy (active high)
39 m pd178p018 a/d converter characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit conversion total 3.0 lsb error conversion time t conv 22.2 44.4 m s sampling time t samp 15/f xx m s analog input v ian 0v dd v voltage remarks 1. f xx : system clock frequency (f x /2) 2. f x : system clock oscillation frequency pll characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit operating f in1 vcol pin mf mode sine wave input v in = 0.1 v p-p 0.5 3 mhz frequency f in2 vcol pin hf mode sine wave input v in = 0.2 v p-p 9 55 mhz f in3 vcoh pin vhf mode sine wave input v in = 0.15 v p-p 60 160 mhz ifc characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol test conditions min. typ. max. unit operating f in4 amifc pin amif count mode 0.4 0.5 mhz frequency sine wave input v in = 0.1 v p-p note f in5 fmifc pin fmif count mode 10 11 mhz sine wave input v in = 0.1 v p-p note f in6 fmifc pin amif count mode 0.4 0.5 mhz sine wave input v in = 0.1 v p-p note note the condition of a sine wave input of v in = 0.1 v p-p is the standard value for operation of this device during stand-alone operation, so in consideration of the effect of noise, it is recommended that operation be at an input amplitude condition of v in = 0.15 v p-p .
40 m pd178p018 prom programming characteristics dc characteristics ( 1) prom write mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbo l note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7v dd v dd v input voltage, low v il v il 0 0.3v dd v output voltage, high v oh v oh i oh = C1 ma v dd C 1.0 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a v pp supply voltage v pp v pp 12.2 12.5 12.8 v v dd supply voltage v dd v cc 6.25 6.5 6.75 v v pp supply current i pp i pp pgm = v il 50 ma v dd supply current i dd i cc 50 ma (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol symbo l note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7v dd v dd v input voltage, low v il v il 0 0.3v dd v output voltage, high v oh1 v oh1 i oh = C1 ma v dd C 1.0 v v oh2 v oh2 i oh = C100 m av dd C 0.5 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a output leakage current i lo i lo 0 v out v dd , oe = v ih C10 +10 m a v pp supply voltage v pp v pp v dd C 0.6 v dd v dd + 0.6 v v dd supply voltage v dd v cc 4.5 5.0 5.5 v v pp supply current i pp i pp v pp = v dd 100 m a v dd supply current i dd i cca1 ce = v il , v in = v ih 50 ma note corresponding m pd27c1001a symbol.
41 m pd178p018 parameter symbol symbo l note test conditions min. typ. max. unit address setup time (to pgm )t as t as 2 m s oe set time t oes t oes 2 m s ce setup time (to pgm )t ces t ces 2 m s input data setup time (to pgm )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s input data hold time t dh t dh 2 m s (from pgm - ) data output float delay time t df t df 0 250 ns from oe - v pp setup time (to pgm )t vps t vps 1.0 ms v dd setup time (to pgm )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms valid data delay time from oe t oe t oe 1 m s oe hold time t oeh 2 m s parameter symbol symbo l note test conditions min. typ. max. unit address setup time (to oe )t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to oe )t ces t ces 2 m s input data setup time (to oe )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s t ahl t ahl 2 m s t ahv t ahv 0 m s input data hold time (from oe - )t dh t dh 2 m s data output float delay time t df t df 0 250 ns from oe - v pp setup time (to oe )t vps t vps 1.0 ms v dd setup time (to oe )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms valid data delay time from oe t oe t oe 1 m s oe pulse width during data t lw t lw 1 m s latching pgm setup time t pgms t pgms 2 m s ce hold time t ceh t ceh 2 m s oe hold time t oeh t oeh 2 m s ac characteristics (1) prom write mode (a) page program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) (b) byte program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) note corresponding m pd27c1001a symbol.
42 m pd178p018 (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol symbo l note test conditions min. typ. max. unit data output delay time from t acc t acc ce = oe = v il 800 ns address data output delay time ce t ce t ce oe = v il 800 ns data output delay time oe t oe t oe ce = v il 200 ns data output float delay time t df t df ce = v il 060ns from oe - data hold time to address t oh t oh ce = oe = v il 0ns parameter symbol test conditions min. typ. max. unit prom programming mode t sma 10 m s setup time note corresponding m pd27c1001a symbol. (3) prom programming mode setting (t a = 25 c, v ss = 0 v)
43 m pd178p018 prom write mode timing (page program mode) a2 to a16 a0, a1 d0 to d7 v dd v pp v pp v dd v dd + 1.5 v dd v il v ih ce v il v ih pgm v il v ih oe t as page data latch page program program verify data output data input t ahl t ds t dh t vps hi-z hi-z t pgms t ahv t df t ah t oe t oeh t ces t oes t ceh t pw t vds t lw hi-z
44 m pd178p018 prom write mode timing (byte program mode) cautions 1. v dd should be applied before v pp , and removed after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. reliability may be adversely affected if removal/reinsertion is performed while + 12.5 v is being applied to v pp . prom read mode timing a0 to a16 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il program program verify data input data output hi-z hi-z hi-z t df t ah t as t ds t dh t vps t vds t ces t pw t oeh t oes t oe ce v ih v il oe v ih v il d0 to d7 a0 to a16 effective address t ce hi-z data output hi-z t acc note1 t oe note 1 t oh t df note 2 notes 1. if you want to read within the range of t acc , make the oe input delay time from the fall of ce a maximum of t acc C t oe . 2. t df is the time from when either oe or ce first reaches v ih .
45 m pd178p018 prom programming mode setting timing reset 0 v dd v dd 0 v dd v pp a0 to a16 effective address t sma
46 m pd178p018 7. package drawings 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.8?.2 0.031 +0.009 ?.008 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 a 17.2?.4 0.677?.016 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 17.2?.4 0.677?.016 f 0.825 0.032 g 0.825 0.032 h 0.30?.10 0.012 +0.004 ?.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.1?.1 0.004?.004 r5 ? 5 ? +0.10 ?.05 +0.004 ?.003 m m l k j h q p n r detail of lead end i g k 1.6?.2 0.063?.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-4 s 3.0 max. 0.119 max.
47 m pd178p018 z u1 a t b d c u g f w r s q k m i h j x80kw-65a-1 item millimeters inches a b c d f g h i j k q 14.0 0.2 13.6 3.6 max. 0.06 13.6 0.551 0.008 0.072 0.142 max. 0.003 0.024 (t.p.) 0.535 note r s 0.825 0.825 0.65 (t.p.) 0.032 0.032 each lead centerline is located within 0.06 mm (0.003 inch) of its true position (t.p.) at maximum material condition. 0.018 0.535 t r 2.0 r 0.079 0.551 0.008 14.0 0.2 1.84 u 9.0 0.354 u1 2.1 0.083 +0.004 ?.005 w z 0.10 0.004 80 1 0.45 0.10 0.039 +0.007 ?.006 1.0 0.15 c 0.3 c 0.012 0.75 0.15 0.030 +0.006 ?.007 80 pin ceramic wqfn
48 m pd178p018 8. recommended soldering conditions this product should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact an nec sales representa- tive. table 8-1. surface mounting type soldering conditions m pd178p018gc-3b9: 80-pin plastic qfp (14 14 mm, 0.65-mm pitch) package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), number of times: three times max. exposure limit: 7 days note (20 hours pre-baking is required at 125 c afterwards) (points to note) do not bake components in any packaging except heat-resistant trays, that is components in magazines, tape, or non-heat-resistant trays. package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), number of times: three times max. exposure limit: 7 days note (20 hours pre-baking is required at 125 c afterwards) (points to note) do not bake components in any packaging except heat-resistant trays, that is components in magazines, tape, or non-heat-resistant trays. solder bath temperature : 260 c max., duration : 10 sec. max., number of times : once, preheating temperature : 120 c max. (package surface temperature) exposure limit: 7 days note (20 hours pre-baking is required at 125 c afterwards) (points to note) do not bake components in any packaging except heat-resistant trays, that is components in magazines, tape, or non-heat-resistant trays. pin temperature: 300 c max. duration: 3 sec. max. (per pin row) infrared reflow vps wave soldering partial heating ir35-207-3 vp15-207-3 ws60-207-1 recommended condition symbol soldering conditions soldering method note exposure limit before soldering after the dry pack package is opened. storage conditions: 25 c and relative humidity at 65% or less. caution do not use different soldering method together (except for partial heating).
49 m pd178p018 appendix a. development tools the following development tools are available for system development using the m pd178p018 subseries. language processing software ra78k/0 notes 1, 2, 3, 4 78k/0 series common assembler package cc78k/0 notes 1, 2, 3, 4 78k/0 series common c compiler package df178018 notes 1, 2, 3, 4 m pd178018 subseries common device file cc78k/0-l notes 1, 2, 3, 4 78k/0 series common c compiler library source file prom writing tools pg-1500 prom writer pg-178p018gc pa-178p018kk-t pg-1500 controller notes 1, 2 pg-1500 control program debugging tools ie-78000-r in-circuit emulator common to 78k/0 series ie-78000-r-a in-circuit emulator common to 78k/0 series (for the integrated debugger) ie-78000-r-bk break board common to 78k/0 series ie-178018-r-em emulation board common to m pd178018 subseries ep-78230gc-r emulation probe common to m pd78234 subseries ev-9200gc-80 socket for mounting on target system board created for 80-pin plastic qfp (gc-3b9 type) ev-9900 jig used when removing the m pd178p018kk-t from the ev-9200gc-80. sm78k0 notes 5, 6, 7 78k/0 series common system simulator id78k0 notes 4, 5, 6, 7 integrated debugger for ie-78000-r-a sd78k/0 notes 1, 2 ie-78000-r screen debugger df178018 notes 1, 2, 4, 5, 6, 7 m pd178018 subseries device file real-time os rx78k/0 notes 1, 2, 3, 4 78k/0 series real-time os mx78k0 notes 1, 2, 3, 4 78k/0 series os program writer adapters connected to a pg-1500 notes 1. pc-9800 series (ms-dos tm ) based 2. ibm pc/at tm and compatibles (pc dos tm /ibm dos tm /ms-dos) based 3. hp9000 series 300 tm (hp-ux?) based 4. hp9000 series 700 tm (hp-ux tm ) based, sparcstation tm (sunos tm ) based, ews4800 series (ews- ux/v) based 5. pc-9800 series (ms-dos + windows tm ) based 6. ibm pc/at and compatibles (pc dos/ibm dos/ms-dos + windows) based 7. news tm (news-os tm ) based
50 m pd178p018 fuzzy inference development support system fe9000 note 1 /fe9200 note 2 fuzzy knowledge data creation tool ft9080 note 1 /ft9085 note 3 translator fi78k0 notes 1, 3 fuzzy inference module fd78k0 notes 1, 3 fuzzy inference debugger notes 1. pc-9800 series (ms-dos) based 2. ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos + windows) based 3. ibm pc/at and its compatibles (pc dos/ibm dos/ms-dos) based remarks 1. please refer to the 78k/0 series selection guide (u11126e) for information on third party development tools. 2. the ra78k/0, cc78k/0, sd78k/0, id78k/0, sm78k/0, and rx78k/0 are used in combination with the df178018.
51 m pd178p018 a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g1e item millimeters inches a b c d e f g h i j k l m n o p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059 f f based on ev-9200gc-80 (1) package drawing (in mm) f f conversion socket drawing and recommended footprint figure a-1. drawing of ev-9200gc-80 (for reference only)
52 m pd178p018 a f d e c b g j k l h i 0.026 0.748=0.486 0.026 0.748=0.486 ev-9200gc-80-p1e item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 0.65 0.02 19=12.35 0.05 0.65 0.02 19=12.35 0.05 f f +0.001 ?.002 +0.003 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 f +0.001 ?.002 f f based on ev-9200gc-80 (2) pad drawing (in mm) dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution f figure a-2. recommended footprint of ev-9200gc-80 (for reference only)
53 m pd178p018 appendix b. related documents device documents title document no. document no. (japanese) (english) m pd178018 subseries users manual u11410j u11410e 78k/0 series users manualinstruction u12326j ieu-1372 78k/0 series instruction set u10904j 78k/0 series instruction table u10903j m pd178018 subseries special function register table to be prepared 78k/0 series application note basics (ii) u10121j u10121e development tool documents (users manual) title document no. document no. (japanese) (english) ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k/0 c compiler operation u11517j u11517e language u11518j u11518e cc78k/0 c compiler application note programming know-how eea-618 eea-1208 cc78k series library source file u12322j pg-1500 prom programmer u11940j eeu-1335 pg-1500 controller pc-9800 series (ms-dos) based eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos) based eeu-5008 u10540e ie-78000-r u11376j u11376e ie-78000-r-a u10057j u10057e ie-78000-r-bk eeu-867 eeu-1427 ie-178018-r-em u10668j u10668e ep-78230 eeu-985 eeu-1515 sm78k0 system simulator windows based reference u10181j u10181e sm78k series system simulator u10092j u10092e id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e sd78k/0 screen debugger pc-9800 series (ms-dos) based introduction eeu-852 u10539e reference u10952j sd78k/0 screen debugger ibm pc/at (pc dos) based introduction eeu-5024 eeu-1414 reference u11279j u11279e external parts user open interface specifications caution the contents of the above documents are subject to change without notice. please ensure that the latest versions are used in design work, etc.
54 m pd178p018 related documents for embedded software (user?s manual) title document no. document no. (japanese) (english) 78k/0 series realtime os basics u11537j installation u11536j technical u11538j 78k/0 series os mx78k0 basics eeu-5010 fuzzy knowledge data creation tool eeu-829 eeu-1438 78k/0, 78k/ii, 87ad series eeu-862 eeu-1444 fuzzy inference development support systemtranslator 78k/0 series fuzzy inference development support system fuzzy inference module eeu-858 eeu-1441 78k/0 series fuzzy inference development support system eeu-921 eeu-1458 fuzzy inference debugger other documents title document no. document no. (japanese) (english) ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality guides on nec semiconductor devices c11531j c11531e nec semiconductor device reliability and quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 semiconductor device quality assurance guide c11893j c11893e microcomputer-related product guide (products by other manufacturers) u11416j caution the contents of the above documents are subject to change without notice. ensure that the latest versions are used in design work, etc.
55 m pd178p018 [memo]
56 m pd178p018 [memo]
57 m pd178p018 [memo]
58 m pd178p018 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
59 m pd178p018 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
60 m pd178p018 purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. m4 96.5 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. license not needed : m pd178p018kk-t the customer must judge the need for license : m pd178p018gc-3b9

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